pipelined architecture

См. также в других словарях:

• Architecture MIPS — MIPS I R2000 • R3000 MIPS II R6000 MIPS III R4000 • R4200 • R4600 …   Wikipédia en Français

• Hazard (computer architecture) — Hazards are problems with the instruction pipeline in central processing unit (CPU) microarchitectures that potentially result in incorrect computation. There are typically three types of hazards: data hazards structural hazards control hazards… …   Wikipedia

• MIPS architecture — MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a RISC microprocessor architecture developed by MIPS Technologies. As of|1999|alt=By the late 1990s it was estimated that one in three RISC chips produced were …   Wikipedia

• Transport triggered architecture — The transport triggered architecture (TTA) is an application specific instruction set processor ( ASIP ) architecture template that allows easy customization of microprocessor designs. The basic idea of transport triggering is to allow programs… …   Wikipedia

• Decoupled architecture — In computer science, a decoupled architecture is a processor with out of order execution that separates the fetch and decode stages from the execute stage in a pipelined processor by using a buffer. The buffer s purpose is to partition the memory …   Wikipedia

• Microarchitecture — Computer organization redirects here. For organizations that make computers, see List of computer system manufacturers. For one classification of computer architectures, see Flynn s taxonomy. For another classification of instruction set… …   Wikipedia

• Delay slot — In computer architecture, a delay slot is an instruction slot that gets executed without the effects of a preceding instruction. The most common form is a single arbitrary instruction located immediately after a branch instruction on a RISC or… …   Wikipedia

• Digital signal processor — A Digital Signal Processor chip found in a guitar effects unit. A digital signal processor (DSP) is a specialized microprocessor with an architecture optimized for the fast operational needs of digital signal processing.[1] …   Wikipedia

• Cray X-MP — 48 Die Cray X MP war ein Supercomputer, der von Cray Research entwickelt, gebaut und verkauft wurde. Sie war der erste parallele Vektor Prozessor gestützte Computer der Firma und war 1982 der Nachfolger der 1976 erschienenen Cray 1. Sie war von… …   Deutsch Wikipedia

• конвейерная архитектура — — [Л.Г.Суменко. Англо русский словарь по информационным технологиям. М.: ГП ЦНИИС, 2003.] Тематики информационные технологии в целом EN pipelined architecture …   Справочник технического переводчика

• Instruction pipeline — Pipelining redirects here. For HTTP pipelining, see HTTP pipelining. Basic five stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). In the fourth clock… …   Wikipedia